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? 2002 mos integrated circuit document no. s15973ej1v0ds00 (1st edition) date published february 2002 n cp(k) printed in japan the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. description the pd16835a is a monolithic quad h bridge driver ic that employs a cmos control circuit and a mos fet output circuit. because it uses mos fets in its output stage, this driver ic consumes less power than conventional driver ics that use bipolar transistors. because the pd16835a controls a motor by inputting serial data, its package has been shrunk and the number of pins reduced. as a result, the performance of the application set can be improved and the size of the set has been reduced. the pd16835a employs a current-controlled 64-step micro step driving method that drives stepper motor with low vibration. the pd16835a is housed in a 38-pin plastic shrink sop to contribute to the miniaturization of the application set. the pd16835a can simultaneously drive two stepper motors and is ideal for the mechanisms of camcorders. features ? four h bridge circuits employing power mos fets ? current-controlled 64-step micro step driving ? motor control by serial data (8 bytes x 8 bits) (original oscillation: 4-mhz input) data is input with the lsb first. evr reference setting voltage: 100 to 250 mv (@v ref = 250 mv) ... 4-bit data input (10-mv step) chopping frequency: 32 to 124 khz ... 5-bit data input (4-khz step) original oscillation division or internal oscillation selectable number of pulses in 1 v d : 0 to 252 pulses ... 6 bits + 2-bit data input (4 pulses/step) step cycle: 0.25 to 8191.75 s ... 15-bit data input (0.25- s step) ? 3-v power supply. minimum operating voltage: 2.7 v (min.) ? low current consumption i dd : 3.0 ma (max.), i dd (reset) : 100 a (max.), i mo(reset) : 1.0 a (max.) ? 38-pin plastic shrink sop (7.62 mm (300)) ordering information part number package pd16835ags-bgg 38-pin plastic shrink sop (7.62 mm (300))
data sheet s15973ej1v0ds 2 pd16835a block diagram reset osc in osc out v d v ref x 2 sclk sdata latch serial-pararelle decoder pulse generater evr1 1/n selector v m v m v m v m filter filter filter filter osc evr2 current set evr1 evr2 current set extout selector exp0 exp1 exp2 exp3 37 36 32 7 35 34 33 17 18 19 21 v dd v m1 v m2 v m3 v m4 c osc lgnd pgnd 38 8 23 27 9 13 2 1 20 fb a a 1 fb b fb c fb d fil d d 2 d 1 fil c c 2 c 1 fil b b 2 b 1 fil a a 2 25 24 29 15 11 6 ext 31 22 10 12 5 14 16 4 30 28 3 26 + ?+ h bridge 1ch h bridge 2ch h bridge 1ch h bridge 2ch ext + ?+ + ?+ + ?+
data sheet s15973ej1v0ds 3 pd16835a pin configuration 38-pin plastic shrink sop (7.62 mm (300)) lgnd c osc fil a fil b fil c fil d v ref v dd v m3 d 2 fb d d 1 v m4 c 2 fb c c 1 exp0 exp1 exp2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 reset osc out osc in sclk sdata latch v d ext b 2 fb b b 1 v m2 a 2 fb a a 1 v m1 ext exp3 pgnd
data sheet s15973ej1v0ds 4 pd16835a 1. pin functions pin no. symbol function 1 lgnd control circuit gnd pin 2c osc chopping capacitor connection pin 3fil a 1-ch filter capacitor connection pin (1000 pf typ.) 4fil b 2-ch filter capacitor connection pin (1000 pf typ.) 5fil c 1-ch filter capacitor connection pin (1000 pf typ.) 6fil d 2-ch filter capacitor connection pin (1000 pf typ.) 7v ref reference voltage input pin (250 mv typ.) 8v dd control circuit supply voltage input pin 9v m3 output circuit supply voltage input pin 10 d 2 2-ch output pin 11 fb d 2-ch sense resistor connection pin 12 d 1 2-ch output pin 13 v m4 output circuit supply voltage connection pin 14 c 2 1-ch output pin 15 fb c 1-ch sense resistor connection pin 16 c 1 1-ch output pin 17 exp0 output monitor pin (open drain) 18 exp1 output monitor pin (open drain) 19 exp2 output monitor pin (open drain) 20 pgnd power circuit gnd pin 21 exp3 output monitor pin (open drain) 22 ext logic circuit monitor pin 23 v m1 output circuit supply voltage input pin 24 a 1 1-ch output pin 25 fb a 1-ch sense resistor connection pin 26 a 2 1-ch output pin 27 v m2 output circuit supply voltage input pin 28 b 1 2-ch output pin 29 fb b 2-ch sense resistor connection pin 30 b 2 2-ch output pin 31 ext logic circuit monitor pin 32 v d video sync signal input pin 33 latch latch signal input pin 34 sdata serial data input pin 35 sclk serial clock input pin 36 osc in original oscillation input pin (4 mhz typ.) 37 osc out original oscillation output pin 38 reset reset signal output pin
data sheet s15973ej1v0ds 5 pd16835a 2. i/o pin equivalent circuit pin name equivalent circuit pin name equivalent circuit pad pad pad v dd pad v dd pad v dd pad buffer parasitic diodes pad fb v dd v m v dd v dd pull-down resistor (125 ? ) v dd latch sdata sclk osc out ext ext v ref a 1 , a 2 b 1 , b 2 c 1 , c 2 d 1 , d 2 osc in reset exp0 exp1 exp2 exp3 fil a fil b fil c fil d
data sheet s15973ej1v0ds 6 pd16835a 3. example of standard connection reset osc in osc out v d v ref x2 sclk sdata latch serial-pararelle decoder pulse generater evr1 1/n selector v m v m v m v m filter filter filter filter osc regulator evr2 current set evr1 evr2 current set extout selector exp0 exp1 exp2 exp3 v dd v m1 v m2 v m3 v m4 c osc lgnd pgnd fb a a 1 fb b fb c fb d fil d d 2 d 1 fil c c 2 c 1 fil b b 2 b 1 fil a motor 1 motor 2 a 2 ext ext + ? + h bridge 1ch h bridge 2ch h bridge 1ch h bridge 2ch cpu 250 mv evr : 1010 f osc : 64 khz 100 k ? x 4 4 mhz 3.3 v 33 pf battery 4.8 to 11 v 6.8 ? x 2 1000 pf x 2 1000 pf 1000 pf 6.8 ? 6.8 ? + ? + + ? + + ? +
data sheet s15973ej1v0ds 7 pd16835a 4. standard characteristics curves p t vs. t a characteristics i mo (reset) vs. v m characteristics 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 total power dissipation p t (w) ambient temperature t a ( c) 80 100 120 125 c/w 1 0.8 0.6 0.4 0.2 0 468 output circuit supply voltage v m (v) 10 12 off v m pin current i mo (reset) ( a) t a = 25 c, no load, after reset i dd vs. v dd characteristics 5 4 3 2 1 0 234 control circuit supply volage v dd (v) 56 v dd pin current i dd (ma) i dd (reset) vs. v dd characteristics 200 150 100 50 0 234 control circuit supply volage v dd (v) 56 v dd pin current at reset state i dd (reset) ( a) t a = 25 c, operating, output open v ih /v dd , v il /v dd vs. v dd characteristics 1 0.8 0.6 0.4 0.2 0 234 control circuit supply volage v dd (v) 56 input voltage v ih /v dd , v il /v dd (v) t a = 25 c v il t a = 25 c, after reset v ih i ih /i il vs. v in characteristics 60 40 20 0 234 input voltage v in (v) 56 high-level/low-level input current i ih /i il ( a) t a = 25 c, i ih : v in = v dd , i il : v in = 0 v i il i ih 20 40 60 ? 10 0
data sheet s15973ej1v0ds 8 pd16835a f osc vs. v dd characteristics f step vs. v dd characteristics 150 140 130 120 110 100 90 chopping frequency f osc (khz) 23456 control circuit supply voltage v dd (v) 6 5 4 3 2 234 control circuit supply voltage v dd (v) 56 step frequency f step (khz) t a = 25 c, c osc = 100 pf i m (max) vs. evr characteristics 80 70 60 50 40 30 20 50 100 150 200 250 300 reference setting voltage evr (mv) sine wave peak output current i m (max) (ma) t a = 25 c, c osc = 100 pf, data: all high t on , t off vs. v m characteristics 500 400 300 200 100 0 468 output circuit supply voltage v m (v) 10 12 turn-on time, turn-off time t on /t off (ns) t a = 25 c, v m = 6 v rs = 6.8 ? , f osc = 64 khz, l = 25 mh/r = 100 ? at 1 khz v refver vs. v dd characteristics 40 30 20 10 0 234 control circuit supply voltage v dd (v) 56 evr variable voltage v refver (mv) t a = 25 c, v ref = 250 mv t a = 25 c, i m = 100 ma, c fil : none t on t off
data sheet s15973ej1v0ds 9 pd16835a 5. interface (i/f) circuit data configuration (f clk = 4-mhz external clock input) input data consists of serial data (8 bytes x 8 bits). input serial data with the lsb first, from the 1st byte to 8th byte. (1) initial data (2) standard data <1st byte> <1st byte> bit data function setting bit data function setting d7 1 header data2 d7 0 header data2 d6 1 header data1 d6 0 header data1 d5 1 header data0 data selection d5 0 header data0 data selection d4 0 ?? d4 0 ?? d3 1 or 0 exp3 hi-z or l d3 1 or 0 exp3 hi-z or l d2 1 or 0 exp2 hi-z or l d2 1 or 0 exp2 hi-z or l d1 1 or 0 exp1 hi-z or l d1 1 or 0 exp1 hi-z or l d0 1 or 0 exp0 hi-z or l d0 1 or 0 exp0 hi-z or l remark hi-z : high impedance, l : low level (current sink) remark hi-z : high impedance, l : low level (current sink) <2nd byte> <2nd byte> bit data function setting bit data function setting d7 d7 1 or 0 rotation ch ccw/cw d6 d6 1 or 0 enable ch on/off d5 d5 d4 d4 d3 d3 d2 d2 d1 d1 d0 8-bit data input note first point wait start point wait 256 s to 65.28 ms setting (1 to 255) ? t = 256 s d0 6-bit data input pulse number ch number of pulses in 1 v d setting (0 to 63) ? n = 4 pulses note note input other than ? 0 ? . note the number of pulses can be varied in 4-pulse steps. <3rd byte> <3rd byte> bit data function setting bit data function setting d7 d7 d6 d6 d5 d5 d4 d4 d3 d3 d2 d2 d1 d1 d0 8-bit data input note first point magnetize wait start point drive wait 256 s to 65.28 ms setting (1 to 255) ? t = 256 s d0 15-bit data low-order 8-bit data input pulse width ch pulse cycle 0.25 to 8191.75 s setting (1 to 32767) ? t = 0.25 s note input other than ? 0 ? .
data sheet s15973ej1v0ds 10 pd16835a <4th byte> <4th byte> bit data function setting bit data function setting d7 1 or 0 oscsel internal/external d7 1 or 0 current set set2/set1 d6 0 - - d6 d5 0 - - d5 d4 d4 d3 d3 d2 d2 d1 d1 d0 5-bit data input chopping frequency chopping frequency : 32 to 124 khz setting (8 to 31) note ? f = 4 khz d0 15-bit data high-order 8-bit data input pulse width ch pulse cycle : 0.25 to 8191.75 s setting (1 to 32767) ? t = 0.25 s note the frequency is 0 khz if 0 to 7 is input. <5th byte> <5th byte> bit data ext ext bit data function setting d7 0 - - d7 1 or 0 rotation ch ccw/cw d6 note 5 enable note1 enable note1 d6 1 or 0 enable ch on/off d5 note 5 rotation note2 rotation note2 d5 d4 note 5 pulse out pulse out d4 d3 note 5 ff7 ff7 d3 d2 note 5 ff3 ff3 d2 d1 note 5 checksum note3 ff2 d1 d0 note 5 chopping note4 ff1 d0 6-bit data input pulse number ch number of pulses in 1 v d setting (1 to 63) ? n = 4 pulses note notes 1. h level : conducts, l level : stops 2. h level : reverse (ccw), l level : forward (cw) 3. h level : normal data input, l level : abnormal data input 4. not output in internal oscillation mode. 5. select one of d0 to d6 and input ? 1 ? . if two or more of d0 to d6 are selected, they are positively ored for output. note the number of pulses can be varied in 4-pulse steps. <6th byte> <6th byte> bit data function setting bit data function setting d7 d7 d6 d6 d5 d5 d4 4-bit data input ch current set2 ch output current setting 2 evr : 100 to 250 mv setting (0 to 15) note d4 d3 d3 d2 d2 d1 d1 d0 4-bit data input ch current set1 ch output current setting 1 evr : 100 to 250 mv setting (0 to 15) note d0 15-bit data low-order 8-bit data input pulse width ch pulse cycle: 0.25 to 8191.75 s setting (1 to 32767) ? t = 0.25 s note a voltage of about double evr is output to the fil pin.
data sheet s15973ej1v0ds 11 pd16835a <7th byte> <7th byte> bit data function setting bit data function setting d7 d7 1 or 0 current set set2/set1 d6 d6 d5 d5 d4 4-bit data input ch current set2 ch output current setting 2 evr: 100 to 250 mv setting (0 to 15) note d4 d3 d3 d2 d2 d1 d1 d0 4-bit data input ch current set1 ch output current setting 1 evr: 100 to 250 mv setting (0 to 15) note d0 15-bit data high-order 7-bit data input pulse width ch pulse cycle: 0.25 to 8191.75 s setting (1 to 32767) ? t = 0.25 s note a voltage of about double evr is output to the fil pin. <8th byte> <8th byte> bit data function setting bit data function setting d7 1 or 0 d7 1 or 0 d6 1 or 0 d6 1 or 0 d5 1 or 0 d5 1 or 0 d4 1 or 0 d4 1 or 0 d3 1 or 0 d3 1 or 0 d2 1 or 0 d2 1 or 0 d1 1 or 0 d1 1 or 0 d0 1 or 0 checksum checksum note d0 1 or 0 checksum checksum note note data is input so that the sum of the 1st through the 8th bytes is 00h. note data is input so that the sum of the 1st through the 8th bytes is 00h.
data sheet s15973ej1v0ds 12 pd16835a data configuration data can be input in either of two ways. initial data can be input when the power is first applied, or standard data can be input during normal operation. input serial data with the lsb first, i.e., starting from the d0 bit (lsb) of the 1st byte. therefore, the d7 bit of the 8th byte is the most significant bit (msb). when inputting initial data, set a start point wait time that specifies the delay from power application to pulse output, and the start point drive wait time. at the same time, also set a chopping frequency and a reference voltage (evr) that determines the output current of each channel. because the pd16835a has an ext pin for monitoring the internal operations, the parameter to be monitored can be selected by initial data. when inputting standard data, input the rotation direction of each channel, the number of pulses, and the data for the pulse cycle. initial data or standard data is selected by using bits d5 to d7 of the 1st byte (see table 5-1). table 5-1. data selection mode (1st byte) d7 d6 d5 data type 1 1 1 initial data 0 0 0 standard data remark if the high-order three bits are high, the initial data is selected; if they are low, the standard data is selected. data other than (0, 0, 0) and (1, 1, 1) must not be input. input the serial data during start point wait time. details of data configuration how to input initial data and standard data is described below. (1) initial data input <1st byte> the 1st byte specifies the type of data (initial data or standard data) and determines the presence or absence of the exp pin output. bits d5 to d7 of this byte specify the type of data as shown in table 5-1, while bits d0 to d3 select the exp output (open drain). table 5-2. 1st byte data configuration bit d7d6d5d4d3d2d1d0 data 1 1 1 0 0 or 1 0 or 1 0 or 1 0 or 1 the exp pin goes low (current sink) when the input data is ? 0 ? , and high (high impedance state) when the input data is ? 1 ? . pull this pin up to v dd for use. input ? 0 ? to bit d4.
data sheet s15973ej1v0ds 13 pd16835a <2nd byte> the 2nd byte specifies the delay between data being read and data being output. this delay is called the start up wait time, and the motor can be driven from that point at which the start up wait time is ? 0 ? . this time is counted at the rising edge of v d . the start up wait time can be set to 65.28 ms (when a 4-mhz clock is input), and can be fine-tuned by means of 8-bit division (256- s step: with 4-mhz clock). the start up wait time is set to 65.28 ms when all the bits of the 2nd byte are set to ? 1 ? . caution always input data other than ?0? to this byte because the start up wait time is necessary for latching data. if ?0? is input to this byte, data cannot be updated. transfer standard data during the start up wait time. <3rd byte> the 3rd byte specifies the delay between the start point wait time being cleared and the output pulse being generated. this time is called the start up drive wait time, and the output pulse is generated from the point at which the start up drive wait time reaches ? 0 ? . the start up drive wait time is counted at the falling edge of the start up wait time. the start up drive wait time can be set to 65.28 ms (with 4-mhz clock) and can be fine-tuned by means of 8-bit division (256- s step: with 4-mhz clock). the start up drive wait time is set to 65.28 ms when all the bits of the 3rd byte are ? 1 ? . caution always input data other than ?0? to this byte because the start up drive wait time is necessary for latching data. if ?0? is input to this byte, data cannot be updated. <4th byte> the 4th byte selects a chopping frequency by using 5-bit data. it also selects whether the chopping frequency is created by dividing the original oscillation (external clock) or whether the internal oscillator is used. the chopping frequency is selected by bits d0 to d4. bit d7 specifies the method used to create the chopping frequency. when this bit is ? 0 ? , the original oscillation (external clock input to osc in ) is used; when it is ? 1 ? , the internal oscillator is used. bits d5 and d6 are fixed to ? 0 ? . the chopping signal is output after the initial data has been input and the first standard data has been latched (see timing chart ). table 5-3. 4th byte data configuration (initial data) bit d7d6d5d4d3d2d1d0 data 0 or 1 0 0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 the chopping frequency is set to 0 khz and to a value in the range of 32 to 124 khz (in 4-khz steps), as follows. although the chopping frequency is set by 5 bits of data, it is internally configured using 7-bit data (with the low- order 2 bits fixed to 0).
data sheet s15973ej1v0ds 14 pd16835a bitd7d6d5d4d3d2d1 d0 data0 or 1000000 0 f osc = 0 khz bit d7d6d5d4d3d2d1 d0 data0 or 1000011 1 f osc = 0 khz bit d7d6d5d4d3d2d1 d0 data 0 or 1 0 0 0 1 0 0 0 f osc = 32 khz bit d7d6d5d4d3d2d1 d0 data0 or 1000100 1 f osc = 36 khz bit d7d6d5d4d3d2d1 d0 data0 or 1001111 1 f osc = 124 khz <5th byte> the 5th byte selects a parameter to be output to the ext pin (logic operation monitor pin). input data to bits d0 to d6 of this byte. bit d7 is fixed to ? 0 ? . there are two ext pins. ext indicates the operating status of ch, and ext indicates that of ch. the relationship between each bit and each ext pin is as shown in table 5-4. table 5-4. 5th byte data configuration (initial data) bit data ext ext d7 0 not used not used d6 0 or 1 enable enable d5 0 or 1 rotation rotation d4 0 or 1 pulseout pulseout d3 0 or 1 ff7 ff7 d2 0 or 1 ff3 ff3 d1 0 or 1 checksum ff2 d0 0 or 1 chopping ff1 the checksum bit is cleared to ? 0 ? in the event of an error. normally, it is ? 1 ? . if two or more signals that output signals to ext and ext are selected, they are positively ored for output. caution the chopping signal is not output in internal oscillation mode.
data sheet s15973ej1v0ds 15 pd16835a remark the meanings of the symbols listed in table 5-4 are as follows: enable : output setting (h : conducts, l : stops) rotation : rotation direction (h : reverse (ccw), l : forward (cw)) pulseout : output pulse signal ff7 : presence/absence of pulse in latch cycle (outputs h level if output pulse information exists in standard data.) ff3 : pulse gate (output while pulse exists) ff2 : outputs h level during start up wait time + start up drive wait time ff1 : outputs h level during start up wait time checksum : checksum output (h : when normal data is transmitted, l : when abnormal data is transmitted) chopping : chopping wave output (in original oscillation mode only) <6th byte> the 6th byte sets the peak output current value of ch. the output current is determined by the evr reference voltage. the 250-mv (typ.) voltage input from an external source to the v ref pin is internally doubled and input to a 4-bit d/a converter. by dividing this voltage by 4-bit data, an evr reference voltage can be set inside the ic within the range of 200 to 500 mv, in units of 20 mv. the pd16835a can set two values of the evr reference voltage in advance. this is done by using bits d0 to d3 or d4 to d7. which of the two evr reference voltage values is to be used is specified by the current set bit in the standard data. if all the bits of the 6th byte are ? 0 ? , the evr reference voltage of 200 mv is selected; if they are ? 1 ? , the evr reference voltage of 500 mv is selected. table 5-5. 6th byte data configuration (initial data) bit d7d6d5d4d3d2d1d0 data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 remark bits d4 to d7 : reference voltage 2 (evr 2 ) bits d0 to d3 : reference voltage 1 (evr 1 ) <7th byte> the 7th byte specifies the peak output current value of ch. the output current is determined by the evr reference voltage. the 250-mv (typ.) voltage input from an external source to the v ref pin is internally doubled and input to a 4-bit d/a converter. by dividing this voltage by 4-bit data, an evr reference voltage can be set inside the ic within a range of 200 to 500 mv, in units of 20 mv. the pd16835a can set two values of the evr reference voltage in advance. this is done using bits d0 to d3 or d4 to d7. which of the two evr reference voltage values is to be used is specified by the current set bit in the standard data. if all the bits of the 7th byte are ? 0 ? , the evr reference voltage of 200 mv is selected; if they are ? 1 ? , the evr reference voltage of 500 mv is selected.
data sheet s15973ej1v0ds 16 pd16835a table 5-6. 7th byte data configuration (initial data) bit d7d6d5d4d3d2d1d0 data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 remark bits d4 to d7 : reference voltage 2 (evr 2 ) bits d0 to d3 : reference voltage 1 (evr 1 ) <8th byte> the 8th byte is checksum data. normally, the sum of the 8-byte data is 00h. if the sum is not 00h because data transmission is abnormal, the stepping operation is inhibited and the checksum output pin (ext pin) is kept ? l ? . (2) standard data input <1st byte> the 1st byte specifies the type of data and whether the exp pin output is used, such as when the initial data is input. table 5-7. 1st byte data configuration bit d7d6d5d4d3d2d1d0 data 1 1 1 0 0 or 1 0 or 1 0 or 1 0 or 1 the exp pin goes low (current sink) when the input data is ? 0 ? , and high (high impedance state) when the input data is ? 1 ? . input ? 0 ? to bit d4. <2nd byte> the 2nd byte specifies the rotation direction of the channel, enables output of the channel, and the number of pulses (252 pulses max.) during the 1v d period (in 1 cycle of ff2) of the channel. bit d7 is used to specify the rotation direction. the rotation is in the forward direction (cw mode) when this bit is ? 0 ? ; it is in the reverse direction (ccw mode) when the bit is ? 1 ? . bit d6 is used to enable the output of the channel. the channel enters the high impedance state when this bit is ? 0 ? ; it is in conduction mode when the bit is ? 1 ? . the number of pulses is set by bits d0 to d5. it is set by 6 bits in terms of software. however, the actual circuit uses an 8-bit counter with the low-order two bits fixed to ? 0 ? . therefore, the number of pulses that is actually generated during start up wait time + start up drive wait (ff2) cycle is the number of pulses input x 4. the number of pulses can be set to a value in the range of 0 to 252, in units of 4 pulses.
data sheet s15973ej1v0ds 17 pd16835a table 5-8. 2nd byte data configuration (standard data) bit d7d6d5d4d3d2d1d0 data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 rotation direction enable number of pulses <3rd and 4th bytes> the 3rd and 4th bytes select the pulse cycle of the channel and which of the two reference voltages, created in the initial mode, is to be used (current set ). the pulse cycle is specified using 15 bits : bits d0 (least significant bit) to d7 of the 3rd byte, and bits d0 to d6 (most significant bit) of the 4th byte. the pulse cycle can be set to a value in the range of 0.25 to 8191.75 s in units of 0.25 s (with a 4-mhz clock). current set is specified by bit d7 of the 4th byte. when this bit is ? 0 ? , reference voltage 1 (evr 1 ) is selected; when it is ? 1 ? , reference voltage 2 (evr 2 ) is selected. for further information, refer to the description of the 6th byte of the initial data. table 5-9. 4th byte data configuration (standard data) table 5-10. 3rd byte data configuration (standard data) bit d7d6d5d4d3d2d1d0 d7d6d5d4d3d2d1d0 data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 current set most significant bit least significant bit (reference) 6th byte data configuration for initial data bit d7d6d5d4d3d2d1d0 data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 remark bits d4 to d7 : reference voltage 2 (evr 2 ) bits d0 to d3 : reference voltage 1 (evr 1 ) <5th byte> the 5th byte specifies the rotation direction of the channel, enables output of the channel, and the number of pulses (252 pulses max.) during the 1v d period (in one cycle of ff2) of the channel. bit d7 is used to specify the rotation direction. the rotation is in the forward direction (cw mode) when this bit is ? 0 ? ; it is in the reverse direction (ccw mode) when the bit is ? 1 ? . bit d6 is used to enable the output of the channel. the channel goes into a high impedance state when this bit is ? 0 ? ; it is in the conduction mode when the bit is ? 1 ? . the number of pulses is set by bits d0 to d5. it is set by six bits in terms of software. however, the actual circuit uses an 8-bit decoder with the low-order two bits fixed to ? 0 ? . therefore, the number of pulses that is actually generated during start up wait time + start up drive wait (ff2) cycle is the number of pulses input x 4. the number of pulses can be set in a range of 0 to 252 and in units of 4 pulses.
data sheet s15973ej1v0ds 18 pd16835a table 5-11. 5th byte data configuration (standard data) bit d7d6d5d4d3d2d1d0 data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 rotation direction enable number of pulses <6th and 7th bytes> the 6th and 7th bytes select the pulse cycle of the channel and which of the two reference voltages, created in the initial mode, is to be used (current set ). the pulse cycle is specified using 15 bits : bits d0 (least significant bit) to d7 of the 6th byte, and bits d0 to d6 (most significant bit) of the 7th byte. the pulse cycle can be set to a value in the range of 0.25 to 8191.75 s in units of 0.25 s (with a 4-mhz clock). current set is specified by bit d7 of the 7th byte. when this bit is ? 0 ? , reference voltage 1 (evr 1 ) is selected; when it is ? 1 ? , reference voltage 2 (evr 2 ) is selected. for further information, refer to the description of the 7th byte of the initial data. table 5-12. 7th byte data configuration (standard data) table 5-13. 6th byte data configuration (standard data) bit d7d6d5d4d3d2d1d0 d7d6d5d4d3d2d1d0 data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 current set most significant bit least significant bit (reference) 7th byte data configuration for initial data bit d7d6d5d4d3d2d1d0 data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 remark bits d4 to d7 : reference voltage 2 (evr 2 ) bits d0 to d3 : reference voltage 1 (evr 1 ) <8th byte> the 8th byte is checksum data. normally, the sum of the 8-byte data is 00h. if the sum is not 00h because data transmission is abnormal, the stepping operation is inhibited and the checksum output pin (ext pin) is held at ? l ? .
data sheet s15973ej1v0ds 19 pd16835a (data update timing) the standard data (pulse width, number of pulses, rotation direction, current setting, and enable) of this product are set and updated at the following latch timing. table 5-14. data update timing enable change 1 10 11 00 0 pulse width ff2 ff2 ff2 ? number of pulses ff2 ff2 ff2 ? rotation direction ff2 ff2 ff2 ? current setting ff2 ff1 ff2 ? enable ff2 ff1 ff2 ? the timing at which data is to be updated differs, as shown in table 5-14, depending on the enabled status. for example, suppose the enable signal is currently ? 0 ? (output high impedance) and ? 1 ? (output conduction) is input by the next data. in this case, the pulse width, number of pulses, and rotation direction signals are updated at ff2(upon the completion of start up wait), and the current setting and enable signals are updated at ff1 (upon completion of start up drive wait). v d ff1 start up wait ff2 start up wait + start up drive wait pulse output v d latch i1 pulse width, number of pulses, and rotation direction are updated. current setting and enable are updated (enable change: 0 to 1). initial data identification (1) s1 (2) s2 (3) s3 standard data identification i1 data is output. ff1, ff2 output
data sheet s15973ej1v0ds 20 pd16835a (1) (2) (3) pulse width internal data retained. output reset not output rotation direction internal output retained not output number of pulses internal data retained. output reset not output updated to s2 data at ff2 current setting internal output retained not output enable internal output retained not output updated to s2 data at either ff1 or ff2 by enable data of (2) the initial mode of this product is as follows. the ic operation can be initialized as follows: (1) turns on v dd . (2) make reset input ? l ? . (3) input serial initial data. in initial mode, the operating status of the ic is as shown in table 5-15. table 5-15. operations in initial mode item specifications current consumption 100 a osc oscillation stops. input of external clock is inhibited. v d input inhibited. ff1 to ff7 ? l ? level pulse out ? l ? level exp0 to exp3 undefined in the case of (1) above. previous value is retained in the case of (2) above. can be updated by serial data in the case of (3) above. serial operation can be accessed after initialization in the case of (1) above. can be accessed after reset has gone ? h ? in the case of (2) above. can be accessed in the case of (3) above. step pulse output is inhibited and ff7 is made ? l ? if the following conditions are satisfied. (1) if the set number of pulses (2nd/5th: standard data) is 00h. (2) if the checksum value is other than 00h. (3) if the start up wait time is set to 1 v d or longer. (4) if the start up wait time + start up drive wait time is set to 1 v d or longer. (5) if start up wait is completed earlier than latch ( ). (6) if v d is not input.
data sheet s15973ej1v0ds 21 pd16835a cautions on correct use (1) with this product, input the data for start up wait and start up drive wait. because the standard data are set or updated by these wait times, if the start up wait time and start up drive wait time are not input, the data are not updated. (2) the start up wait time must be longer than latch. (3) if the rising of the start up drive wait time is the same as the falling of the last output pulse, a count error occurs, and the ic may malfunction. (4) input the initial data in a manner that it does not straddle the video sync signal (v d ). if it does, the initial data is not latched. (5) transmit the standard data during the start up wait time (ff1). if it is input at any other time, the data may not be transmitted correctly. (6) if the lgnd potential is undefined, the data may not be input correctly. keep the lgnd potential to the minimum level. it is recommended that lgnd and pgnd be divided for connection (single ground) to prevent the leakage of noise from the output circuit.
data sheet s15973ej1v0ds 22 pd16835a 6. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol condition rating unit v dd ? 0.5 to +6.0 v supply voltage v m ? 0.5 to +11.2 v input voltage v in ? 0.5 to v dd + 0.5 v reference voltage v ref 500 mv h bridge drive current note 1 i m(dc) dc 150 ma/phase instantaneous h bridge drive current note 1 i m(pulse) pw 10 ms, duty 5% 300 ma/phase power consumption note 2 p t 1.0 w peak junction temperature t ch(max.) 150 c storage temperature t stg ? 55 to +150 c notes 1. permissible current per phase with the ic mounted on a pcb. 2. when the ic is mounted on a glass epoxy pcb (10 cm x 10 cm x 1 mm). caution if the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. be sure to use the product within the range of the absolute maximum ratings. recommended operating range parameter symbol min. typ. max. unit v dd 2.7 5.5 v supply voltage v m 4.8 11 v input voltage v in 0v dd v reference voltage v ref 225 250 275 mv exp pin input voltage v expin v dd v exp pin input current i expin 100 a h bridge drive current i m(dc) ? 100 +100 ma h bridge drive current i m(pulse) note 1 ? 200 +200 ma clock frequency (osc in )f clk note 2 3.9 4 4.2 mhz clock frequency amplitude v fclk note 2 0.7 v dd v dd v serial clock frequency (sclk) f sclk 5.0 mhz video sync signal width pw (vd) note 3 250 ns latch signal wait time t (vd-latch) note 4 400 ns sclk wait time t (sclk-latch) note 4 400 ns sdata setup time t setup note 4 80 ns sdata hold time t hold note 4 80 ns chopping frequency f osc note 3 32 124 khz reset signal pulse width t rst 100 s operating temperature t a ? 10 +70 c peak junction temperature t ch(max.) 125 c notes 1. pw 10 ms, duty 5% 2. c osc = 33 pf, v ref = 250 mv 3. f clk = 4 mhz 4. serial data delay time(see the figure on the next page.)
data sheet s15973ej1v0ds 23 pd16835a v d latch sclk latch sclk sdata d1 d2 d3 t (vd-latch) t (sclk-latch) t (sclk-latch) t setup t hold 64 clocks (8 bits x 8 bytes) t (sclk-latch) ignored because latch is at l level. ignored because latch is at l level. 50% 50% 50%
data sheet s15973ej1v0ds 24 pd16835a electrical characteristics dc characteristics (unless otherwise specified, v dd = 3.3 v, v m = 6.0 v, v ref = 250 mv, t a = 25 c, f clk = 4 mhz, c osc = 33 pf, c fil = 1000 pf, evr = 100 mv (0000)) parameter symbol condition min. typ. max. unit off v m pin current i mo(reset) no load, reset period 1.0 a v dd pin current i dd output open 3.0 ma v dd pin current i dd(reset) reset period 100 a high level input voltage v ih 0.7 v dd v low level input voltage v il 0.3 v dd v input hysteresis voltage v h latch, sclk, sdata, v d , reset, osc in 300 mv v om (h) , v om (h) 5th byte 0.9 v dd v monitor output voltage 1 (ext , ) v om (l) , v om (l) 5th byte 0.1 v dd v v oexp(h) pull up (v dd )v dd v monitor output voltage 2 (exp0 to exp3 : open drain) v oexp(l) i oexp = 100 a 0.1 v dd v high level input current i ih v in = v dd 0.06 ma low level input current i il v in = 0 v ? 1.0 a reset pin high level input current i ih(rst) v rst = v dd 1.0 a reset pin low level input current i il(rst) v rst = 0 ? 1.0 a input pull down resistor r ind latch, sclk, sdata, v d 50 200 k ? h bridge on resistance note 1 r on i m = 100 ma 3.5 5.0 ? f osc(1) data: 00000 (4th byte) 0 chopping frequency (internal oscillation: c osc = 100 pf) f osc(2) data: 11111 (4th byte) 100 124 150 khz step frequency f step minimum step 4 khz v d delay time note 2 ? t vd 250 ns sine wave peak output current note 3 i m l = 25 mh/r = 100 ? (1 khz) evr = 200 mv (1010) r s = 6.8 ? , f osc = 64 khz 52 ma fil pin voltage note 4 v evr evr = 200 mv (1010) 370 400 430 mv fil pin step voltage note 4 v evrstep minimum step 20 mv ac characteristics (unless otherwise specified, v dd = 3.3 v, v m = 6.0 v, t a = 25 c, f clk = 4 mhz) parameter symbol condition min. typ. max. unit h bridge output circuit turn on time t onh i m = 100 ma note 5 1.0 2.0 s h bridge output circuit turn off time t offh i m = 100 ma note 5 1.0 2.0 s notes 1. total of on resistance at top and bottom of output h bridge 2. by osc in and v d sync circuit 3. fb pin is monitored. 4. fil pin is monitored. a voltage about twice that of the evr value is output to the fil pin. 5. 10 to 90% of the pulse peak value without filter capacitor (c fil )
data sheet s15973ej1v0ds 25 pd16835a timing chart (1) notes 1. enable is set at the falling edge of ff1 when the level changes from low to high, and at the falling edge of ff2 when the level changes from high to low. 2. ff7 is an output signal that is used to check for the presence or absence of a pulse in the standard data, is updated at the falling edge of latch and reset once at the rising edge of latch. if check sum is other than ? 00h ? , ff7 goes low, inhibiting pulse output, even if a pulse is generated. 3. check sum output is updated at the falling edge of latch. reset v d latch data osc out (original oscillation) start point wait (ff1) start point wait + start point drive wait (ff2) enable out note 1 chopping pulse exp0 to exp3 pulse out pulse gate (ff3) pulse check note 2 (ff7) check sum note 3 sclk sdata 1st byte 8th byte initialization initial i 1 standard s 1 standard s 2 dummy data exp: 1 exp : 0 enable: 0 exp : 1 enable: 1 standard s 4 exp : 0 enable: 1 standard s 5 exp : 1 enable: 0 standard s 3 exp : 1 error data input at rising edge of reset output by i1 data output by chopping setting of i1 data output by exp setting of i1 data output by exp setting of s1 data output by exp setting of s2data output by i1 data output by s2 data setting output by s5 data setting s 2 data output pulse error enable s 4 data output outputs high level while pulse is being generated outputs high level for standard data while a pulse output signal exists (latch cycle) high level because data is normal. low level because data is abnormal. restore to high level because data is normal. no pulse output because data is erroneous d0 d7 d6 d5 d4 d3 d2 d1 (lsb) data is held at rising edge of sclk.
data sheet s15973ej1v0ds 26 pd16835a timing chart (2) h bridge , 1ch output status h bridge , 2ch output status (cw mode) mob clk (pulse out) clk pulse out h bridge 1ch output status h bridge 2ch output status position no. 1 2 3 cw cw 4565 ccw cw cw ccw 4323 ccw ccw cw cw 4 current direction: a1 a2 current direction: b1 b2 cw mode ccw mode cw mode current direction: a2 a1 current direction: b2 b1 current direction: b2 b1 in cw mode in ccw mode (expanded view) notes1. : position no. is incremented. : position no. is decremented. note1 note1 note2 2. remarks 1. the current value of the actual wave is approximated to the value shown on the next page. 2. the c 1 , c 2 , d 1 , and d 2 pins of channel correspond to the a 1 , a 2 , b 1 , and b 2 pins of channel. 3. the cw mode is set if the d7 bit of the 2nd and 5th bytes of the standard data is ? 0 ? . 4. the ccw mode is set if the d7 bit of the 2nd and 5th bytes of the standard data is ? 1 ? .
data sheet s15973ej1v0ds 27 pd16835a relation between rotation angle, phase current, and vector quantity (64-division micro step) (values of pd16835a for reference) step rotation angle ( ) a phase current b phase current vector quantity min. typ. max. min. typ. max. typ. 00 ? 0 ?? 100 ? 100 1 5.6 2.5 9.8 17.0 ? 100 ? 100.48 2 11.3 12.4 19.5 26.5 93.2 98.1 103 100 3 16.9 22.1 29.1 36.1 90.7 95.7 100.7 100.02 4 22.5 31.3 38.3 45.3 87.4 92.4 97.4 100.02 5 28.1 40.1 47.1 54.1 83.2 88.2 93.2 99.99 6 33.8 48.6 55.6 62.6 78.1 83.1 88.1 99.98 7 39.4 58.4 63.4 68.4 72.3 77.3 82.3 99.97 8 45 65.7 70.7 75.7 65.7 70.7 75.7 99.98 9 50.6 72.3 77.3 82.3 58.4 63.4 68.4 99.97 10 56.3 78.1 83.1 88.1 48.6 55.6 62.6 99.98 11 61.9 83.2 88.2 93.2 40.1 47.1 54.1 99.99 12 67.5 87.4 92.4 97.4 31.3 38.3 45.3 100.02 13 73.1 90.7 95.7 100.7 22.1 29.1 36.1 100.02 14 78.8 93.2 98.1 103 12.4 19.5 26.5 100 15 84.4 ? 100 ? 2.5 9.8 17.0 100.48 16 90 ? 100 ?? 0 ? 100 remark these data do not indicate guaranteed values.
data sheet s15973ej1v0ds 28 pd16835a 7. package drawing 38 20 119 s s a f g e c d n p l j h i k b detail of lead end m m item b c i l m n 38-pin plastic ssop (7.62 mm (300)) a d e f g h j p millimeters 0.65 (t.p.) 0.65 max. 0.10 0.6 0.2 5.6 0.2 0.10 12.7 0.3 0.125 0.075 0.37 1.675 0.125 7.7 0.2 1.55 + 0.05 ? 0.1 1.05 0.2 3 + 7 ? 3 note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. k 0.2 + 0.1 ? 0.05 p38gs-65-bgg-1
data sheet s15973ej1v0ds 29 pd16835a 8. recommended soldering conditions when soldering this product, it is highly recommended to observe the conditions as shown below. if other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. for more details, refer to our document ? semiconductor device mounting technology manual ? (c10535e) . type of surface mount device pd16835ags-bgg: 38-pin plastic shrink sop (7.62 mm (300)) process soldering conditions symbol infrared ray reflow peak temperature: 235 c or below (package surface temperature), reflow time: 30 seconds or less (at 210 c or higher), maximum number of reflow processes: 3 time or less, number of days: none note , flux: rosin-based flux with low chlorine content (chlorine 0.2 wt% or below) is recommended. ir35-00-3 vapor phase soldering peak temperature: 215 c or below (package surface temperature), reflow time: 40 seconds or less (at 200 c or higher), maximum number of reflow processes: 3 time or less, number of days: none note , flux: rosin-based flux with low chlorine content (chlorine 0.2 wt% or below) is recommended. vp15-00-3 wave soldering solder temperature: 260 c or below, flow time: 10 seconds or less, maximum number of flow processes: 1 time, pre-heating temperature: 120 c or below (package surface temperature), flux: rosin-based flux with low chlorine content (chlorine 0.2 wt% or below) is recommended. ws60-00-1 partial heating method pin temperature: 300 c or below, heat time: 3 seconds or less (per each side of the device). ? note number of days the device can be stored after the dry pack has been opened, at conditions of 25 c, 65%rh. caution apply only one kind of soldering condition to a device, except for ? partial heating method ? , or the device will be damaged by heat stress.
data sheet s15973ej1v0ds 30 pd16835a [memo]
data sheet s15973ej1v0ds 31 pd16835a notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd16835a m8e 00. 4 the information in this document is current as of january, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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